1. Field of the Invention
The invention relates to a semiconductor device having a seal ring formed so as to surround a chip region and a mechanism for protecting the seal ring, and a manufacturing method of such a semiconductor device.
2. Related Art
Semiconductor devices are generally produced by providing a multiplicity of ICs (Integrated Circuits), each formed by a plurality of elements and having a predetermined function, in a matrix pattern on a semiconductor wafer such as silicon.
A multiplicity of chip regions provided on the wafer are separated from each other by a lattice-shaped dicing region (scribe lines). After a multiplicity of chip regions are formed on a single wafer through a semiconductor manufacturing process, the wafer is diced along a dicing region into individual chips, whereby semiconductor devices are formed.
When such a wafer is diced into individual chips, chip regions located near a dicing region may be subjected to a mechanical impact. As a result, partial cracks and chippings may be produced in a dicing cross-section of diced chips, that is, semiconductor devices.
A technology generally proposed in view of this problem is to provide a seal ring around a chip region as a ring-shaped protective wall in order to prevent cracks from propagating through the chip region during a dicing process. The seal ring has not only an effect of preventing propagation of cracks during the dicing process but also an effect of preventing moisture and mobile ions from entering from outside the chip.
However, if a part of the seal ring is destroyed due to an impact applied in the dicing process, moisture and mobile ions may enter from outside the chip, and reliability of the chip may not be ensured.
In view of this problem, Japanese Laid-Open Patent Publication No. 2004-79596 (hereinafter, referred to as Patent document 1) proposes a method of forming an opening in a passivation film formed at the topmost surface of a chip. The opening is formed in order to prevent a stress that is applied in a dicing process from propagating through the passivation film into a chip region.
FIG. 20 shows a cross-sectional structure of a conventional semiconductor device having a seal ring (this figure shows a state in which the semiconductor device is formed on a wafer).
As shown in FIG. 20, a plurality of chip regions 142, which will become semiconductor chips by a dicing process, are provided on a semiconductor substrate 111 made of a silicon wafer. The plurality of chip regions 142 are separated from each other by a dicing region 141. A layered structure of an element isolation film 112, a plurality (first through sixth) interlayer insulating films 113 through 118, and a passivation film 119 is formed on the semiconductor substrate 111. An active layer 106 that forms an element such as a transistor is provided in each chip region 142. The active layer 106 is surrounded by the element isolation film 112.
A first via 121 connecting to the active layer 106 is formed in the first interlayer insulating film 113. A first interconnect 122 connecting to the first via 121 is formed in the second interlayer insulating film 114. A second via 123 connecting to the first interconnect 122 is formed in the third and fourth interlayer insulating films 115 and 116, and a second interconnect 124 connecting to the second via 123 is formed in the fourth interlayer insulating film 116. A third via 125 connecting to the second interconnect 124 is formed in the fifth and sixth interlayer insulating films 117 and 118, and a third interconnect 126 connecting to the third via 125 is formed in the sixth interlayer insulating film 118. A pad 127 connecting to the third interconnect 126 is formed in the passivation film 119.
As shown in FIG. 20, a seal ring 143 is formed in a layered structure of the plurality of interlayer insulating films 113 through 118 in the periphery of the chip region 142. The seal ring 143 extends through the layered structure and continuously surrounds the chip region 142. The seal ring 143 is formed by, for example, alternately using an interconnect formation mask and a via formation mask.
More specifically, the seal ring 143 is formed by a conductive film 107 formed in the semiconductor substrate 111, a first seal via 131 formed in the first interlayer insulating film 113 and connecting to the conductive layer 107, a first seal interconnect 132 formed in the second interlayer insulating film 114 and connecting to the first seal via 131, a second seal via 133 formed in the third and fourth interlayer insulating films 115 and 116 and connecting to the first seal interconnect 132, a second seal interconnect 134 formed in the fourth interlayer insulating film 116 and connecting to the second seal via 133, a third seal via 135 formed in the fifth and sixth interlayer insulating films 117 and 118 and connecting to the second seal interconnect 134, and a third seal interconnect 136 formed in the sixth interlayer insulating film 118 and connecting to the third seal via 135. Note that, in the present application, a portion of a seal ring which is formed by an interconnect formation mask is referred to as a seal interconnect, and a portion of a seal ring which is formed by a via formation mask is referred to as a seal via. As shown in Patent document 1, in the passivation film 119, an opening 144 extending to the sixth interlayer insulating film 118 is formed on the dicing region 141 side of the seal ring 143.
Japanese Laid-Open Patent Publication No. 2005-142262 (hereinafter, referred to as Patent document 2), on the other hand, describes that a hollow groove is formed outside a seal ring by embedding an interconnect material (copper) in an interconnect layer and removing the interconnect material by etching, as shown in FIG. 21.